1. Field of the Invention
The present invention relates a method for producing a multilayered ceramic substrate for mounting and interconnecting electronic components such as semiconductor LSI or chip components exterior thereof.
2. Description of the Invention
In these years, a low-temperature firing ceramic multilayered substrate has been developed wherein gold, silver, copper, palladium or their mixtures is used as a conductor material, and such a substrate has been widely used in electronics fields.
The low-temperature firing ceramic multilayered substrate is produced by steps of forming via holes through a ceramic green sheet, filling the via holes with a conductive paste, forming a desired wiring pattern on the green sheet, laminating the desired number of the green sheets to obtain a laminate and firing the laminate.
A material of the low-temperature firing substrate is fired at a temperature of about 850.degree. to 1000 .degree.0 C. since it should be fired at a temperature lower than a melting point of the metal material as described above. As the material of the low-temperature firing substrate, there are a glass-ceramic composite type, a crystallized glass type, a ceramic composite type, and the like. In particular, the glass-ceramic composite type comprising ceramic fillers such as alumina and crystallized glass is often used since it can provide the substrate having various combinations of properties such as a coefficient of thermal expansion, a thermal conductivity, a dielectric constant, etc. by the selection of a glass composition and a kind of the ceramic filler.
There are three kinds of electrodes used for the low-temperature firing multilayered ceramic substrate.
The first one uses a silver layer as an internal electrode of the multilayered substrate and is produce by laminating the desired number of the green sheet having the silver electrode for the low-temperature firing substrate, firing the laminated sheets in an air, printing an electrode pattern with a paste of silver-palladium on the top layer and firing it in the air. This kind of the multilayered substrate uses the silver electrode having a low impedance inside and the silver-palladium mixture which is resistant to soldering heat on the top layer.
The second one uses a silver layer as an internal electrode as in the first one and an electrode pattern of copper on the top layer of the multilayered substrate. Since the copper is used as a wiring pattern on the top layer, the electrode has lower impedance and better solderbility than those of the silver-palladium electrode as described above. However, since copper has a low eutectic point with silver, a low-temperature firing copper paste (e.g. about 600.degree. C.) should be used. As the result, the substrate has some drawbacks such as weak adhesion strength, poor solderbility and the like (see Japanese Patent Publication No. 78798/1991).
The third one uses copper electrodes as an internal electrode and an electrode on a top layer. Though this structure is excellent in the conductor resistance, solderbility and the cost, the firing should be carried out in an inert atmosphere of, for example, nitrogen so that its production is troublesome. In general, for forming the copper electrodes, a wiring pattern should be formed by screen printing with a copper paste on the substrate, drying and firing it at a temperature lower than a melting point of copper (e.g. a firing temperature of about 850.degree. to 950.degree. C.) in a nitrogen atmosphere in which an oxygen partial pressure is so controlled that copper is not oxidized but organic materials in the paste are well burnt off. For the formation of a multilayered structure, a dielectric layer is printed thereon and fired under the same conditions (see Japanese Patent Kokai Publication No. 128899/1980).
However, it is very difficult to control the oxygen partial pressure at a suitable pressure in the firing step. In addition, for the formation of the multilayered structure, firing should be repeated after printing of each paste, so that a lead time becomes long and the production cost including the cost of equipments increases.
Japanese Patent Publication No. 20914/1991 discloses a method for producing a multilayered ceramic substrate using a cupric oxide (CuO) paste and consisting of a step for binder burn-out, a step for reduction and a step for firing. That is, a multilayered body is produced using cupric oxide as a raw material of a conductor, and in the step for binder burn-out, the multilayered body is heated at a temperature sufficient for pyrolysis of the organic binder under an oxygen atmosphere. In the reduction step, cupric oxide is reduced to metal copper and, in the firing step, the substrate is sintered. Thereby, a composition of the atmosphere in the firing step is easily controlled and a dense sintered material is obtained.
The multilayered ceramic substrate shrinks during the firing step. A degree of the shrinkage in accordance with the firing varies with a kind of the substrate material, a composition of the green sheet, a powder lot and the like. This will cause various problems in the production of the multilayered substrate.
Firstly, since the wiring pattern on the top layer is formed after the firing of the internal wiring pattern in the production of the multilayered ceramic substrate as described above, the internal electrode and the wiring pattern on the top layer cannot be connected due to difference in dimensions between them if the shrinkage error of the substrate material is large. As the result, in order to absorb such shrinkage error, a land having an unnecessarily large area should be formed on the top layer electrode, but such an electrode is not suitable for a circuit which requires a dense wiring pattern. Alternatively, various screens for the top wiring patterns are provided according to the specific shrinkage error of the substrate. However, the provision of a number of the screens is not economical.
If the wiring pattern of the top layer is formed at the same time as the formation of the internal electrode, no large land is necessary. However, in this simultaneous formation, the shrinkage error of the substrate still remains. Therefore, a solder paste pattern for mounting the components may not be printed on required positions due to the shrinkage error of the substrate. In addition, a position of the actually mounted component may deviate from a designed position.
Secondly, the multilayered ceramic substrate produced by laminating the green sheets has different shrinkage factors in its longitudinal and lateral directions depending on the sheeting directions of the green sheets. This is one of the problems which arise in the production of the multilayered ceramic substrate.
In order to reduce the shrinkage errors as much as possible, it is necessary to control not only the substrate material and the composition of the green sheet but also the powder lot difference and lamination conditions (e.g. pressing pressure, temperature, etc.). Still, it is said that about .+-.0.5% of the error of the shrinkage factor remains.
This problem is common to the firing substrate made of the ceramics or the glass-ceramics which requires the firing step. Then, if a substrate which shrinks only in a thickness direction of the substrate but does not shrink in a plane direction of the substrate could be produced, the above problems would be solved and such a substrate would be industrially attractive.
To solve the above problems, methods for producing a multilayered ceramic substrate which does not shrink in its plane direction has been disclosed.
U.S. Pat. No. 5,085,720 discloses a method for reducing X-Y shrinkage during firing of green ceramic bodies in which a release layer, which becomes porous during the firing, is placed upon the ceramic body and the assemblage is fired while maintaining pressure on the assemblage normal to the body surface.
Japanese Patent Application No. 243978/1992 also discloses a method for reducing X-Y shrinkage during firing of green ceramic bodies, which method comprises steps of providing a green ceramic body, applying to a surface of the green ceramic body a flexible release layer, firing the assemblage, cooling the fired assemblage and removing the porous layer from the surface of the sintered ceramic body. In this method, pressure is not needed during the firing.
U.S. Pat. No. 5,130,067 discloses a method for producing a multilayered ceramic substrate wherein X-Y shrinkage is controlled and X-Y distortion and Z-direction chamber are eliminated. In this method, laminating a pair of porous green sheets to green ceramic structure prevents X-Y shrinkage during firing of the ceramic structure. After the firing, unsintered porous sheets are removed.
In those methods, the green sheet comprising inorganic material which is not sintered at the firing temperature of the ceramic substrate prevents the ceramic substrate from shrinkage in its plane direction during the firing.
When the firing step is carried out after the green sheet comprising the inorganic material which is not fired at the firing temperature is laminated on either or both surfaces of the laminate, a portion of the inorganic material deposits on the electrode pattern or via electrodes formed on the surface of the glass-ceramic laminate. Such deposition of the inorganic material not only makes surface smoothness of the electrode worse and an electrical resistance of the electrode increased, but also makes solderbility of the electrode worse. Thereby, it is difficult to mount an electronic component on such an electrode. When the inorganic material deposits on only a small area of the electrode, the solderbility may be improved by the removal of the deposit with, for example, polishing. However, this causes a new problem that the number of the steps for the production of the substrate increases. In addition, it is impossible to remove the inorganic material when it is impregnated inside the electrode. When the inorganic material deposits on the via electrode, the electrical resistance of the via electrode is highly increased and electrical communication may not be achieved between the via electrode and an electrode pattern which is formed afterward on the top layer (i.e. a top layer wiring pattern) of the substrate.